With the current popularity of portable communication devices and developed semiconductor fabrication technology, high speed and high performance transistors are more densely integrated on semiconductor dies. Consequently, the amount of heat generated by the semiconductor dies will increase significantly due to the large number of transistors integrated on the semiconductor dies, the large amount of power passing through the transistors, and the high operation speed of the transistors. Accordingly, it is desirable to package the semiconductor dies in a configuration for better heat dissipation.
The field effect transistor (FET) fabricated on silicon-on-insulator (SOI) substrate is widely used in communication applications because of its reliability, a large scale capacity of wafer production, and low cost. SOI technologies at 65 nm or below (45 nm, 22 nm, etc.) need to implement back-gate transistors to improve control over the channel and reduce leakage current.
To accommodate the increased heat generation of high performance dies and to utilize the advantages of FET on SOI, it is therefore an object of the present disclosure to provide an improved semiconductor package design with FETs in a configuration for better heat dissipation. In addition, there is also a need to implement back-gates for FETs to improve control over the channel and reduce leakage current.